High Speed IO Validation Engineer
직군
HW Platform근무지
Rebellions | 리벨리온경기도 성남시 분당구 정자일로156번길 6, R-TOWER 3F ~ 8F
Rebellions’ HW Platform team is seeking a talented and meticulous High Speed IO Validation Engineer to ensure the functional integrity, performance, and compliance of all critical high-speed interfaces within our next-generation AI Chip Ecosystem. This role is essential for delivering ultra-low latency and ultra-high bandwidth systems for our AI Accelerators and Data Center solutions, focusing on comprehensive system-level IO validation and robust system performance.
Responsibilities and Opportunities
- Bring-up and Characterization: Lead the bring-up, electrical characterization, and functional validation of various high-speed interfaces, including SerDes PHYs (PCIe, CXL, Ethernet), High Bandwidth Memory (HBM3E/DDR), and high-speed clocking networks
- Compliance and Interoperability: Conduct thorough compliance and interoperability testing for key industry-standard interfaces to ensure strict adherence to electrical specifications and protocol requirements
- Measurement and Analysis: Perform detailed lab measurements utilizing specialized test equipment (Oscilloscopes, BERTs, VNAs) for jitter analysis, eye diagram analysis, link margin characterization, and system-level margin analysis
- Debugging and Root Cause Analysis: Collaborate cross-functionally with ASIC, SI, and Firmware teams to effectively debug complex IO issues, identify the root cause of performance degradation (e.g., link training failures, marginal timing, BER issues), and drive resolutions
- Documentation: Create detailed test plans, validation reports, and technical documentation summarizing test results, compliance status, and observed failures
Key Qualifications
- Bachelor's or higher degree in Electrical Engineering, or a related field
- Minimum of 5 years of hands-on experience in high-speed IO validation, electrical characterization, and system debug, specifically focused on interfaces operating at multi-Gbps speeds(e.g., 100 Gbps/lane SerDes, HBM/DDR interfaces), including SerDes PHY performance validation such as TX equalization tuning, receiver adaptation, and eye/jitter margin optimization
- Equipment Mastery (Must-Have): Expert proficiency in setting up, operating, and automating high-speed test equipment:
- Real-time/Sampling Oscilloscopes (for Eye and Jitter analysis)
- Vector Network Analyzers (VNA) / Time Domain Reflectometers (TDR)
- Strong working knowledge of physical layer architecture, equalization techniques (CTLE, DFE, FFE), and the operation of high-speed protocols (PCIe, CXL, Ethernet)
- Understanding of firmware/driver architecture and their interaction with hardware systems
전형절차
- 서류전형 > On-line 인터뷰 > On-site 인터뷰 > Culture-fit 인터뷰 > 처우 협의 > 최종 합격
- 전형절차는 직무별로 다르게 운영될 수 있으며, 일정 및 상황에 따라 변동될 수 있습니다.
- 전형 일정 및 결과는 지원 시 작성하신 이메일로 개별 안내드립니다.
참고사항
- 본 공고는 모집 완료 시 조기 마감될 수 있습니다.
- 지원서 내용 중 허위사실이 있는 경우에는 합격이 취소될 수 있습니다.
- 채용 및 업무 수행과 관련하여 요구되는 법령 상 자격이 갖추어지지 않은 경우 채용이 제한될 수 있습니다.
- 보훈 대상자 및 장애인 여부는 채용 과정에서 어떠한 불이익도 미치지 않습니다.
- 담당 업무 범위는 후보자의 전반적인 경력과 경험 등 제반사정을 고려하여 변경될 수 있습니다. 이러한 변경이 필요할 경우, 최종 합격 통지 전 적절한 시기에 후보자와 커뮤니케이션 될 예정입니다.
- 채용 관련 문의사항은 아래 메일 주소로 문의바랍니다.
- [email protected]
공유하기
High Speed IO Validation Engineer
Rebellions’ HW Platform team is seeking a talented and meticulous High Speed IO Validation Engineer to ensure the functional integrity, performance, and compliance of all critical high-speed interfaces within our next-generation AI Chip Ecosystem. This role is essential for delivering ultra-low latency and ultra-high bandwidth systems for our AI Accelerators and Data Center solutions, focusing on comprehensive system-level IO validation and robust system performance.
Responsibilities and Opportunities
- Bring-up and Characterization: Lead the bring-up, electrical characterization, and functional validation of various high-speed interfaces, including SerDes PHYs (PCIe, CXL, Ethernet), High Bandwidth Memory (HBM3E/DDR), and high-speed clocking networks
- Compliance and Interoperability: Conduct thorough compliance and interoperability testing for key industry-standard interfaces to ensure strict adherence to electrical specifications and protocol requirements
- Measurement and Analysis: Perform detailed lab measurements utilizing specialized test equipment (Oscilloscopes, BERTs, VNAs) for jitter analysis, eye diagram analysis, link margin characterization, and system-level margin analysis
- Debugging and Root Cause Analysis: Collaborate cross-functionally with ASIC, SI, and Firmware teams to effectively debug complex IO issues, identify the root cause of performance degradation (e.g., link training failures, marginal timing, BER issues), and drive resolutions
- Documentation: Create detailed test plans, validation reports, and technical documentation summarizing test results, compliance status, and observed failures
Key Qualifications
- Bachelor's or higher degree in Electrical Engineering, or a related field
- Minimum of 5 years of hands-on experience in high-speed IO validation, electrical characterization, and system debug, specifically focused on interfaces operating at multi-Gbps speeds(e.g., 100 Gbps/lane SerDes, HBM/DDR interfaces), including SerDes PHY performance validation such as TX equalization tuning, receiver adaptation, and eye/jitter margin optimization
- Equipment Mastery (Must-Have): Expert proficiency in setting up, operating, and automating high-speed test equipment:
- Real-time/Sampling Oscilloscopes (for Eye and Jitter analysis)
- Vector Network Analyzers (VNA) / Time Domain Reflectometers (TDR)
- Strong working knowledge of physical layer architecture, equalization techniques (CTLE, DFE, FFE), and the operation of high-speed protocols (PCIe, CXL, Ethernet)
- Understanding of firmware/driver architecture and their interaction with hardware systems
전형절차
- 서류전형 > On-line 인터뷰 > On-site 인터뷰 > Culture-fit 인터뷰 > 처우 협의 > 최종 합격
- 전형절차는 직무별로 다르게 운영될 수 있으며, 일정 및 상황에 따라 변동될 수 있습니다.
- 전형 일정 및 결과는 지원 시 작성하신 이메일로 개별 안내드립니다.
참고사항
- 본 공고는 모집 완료 시 조기 마감될 수 있습니다.
- 지원서 내용 중 허위사실이 있는 경우에는 합격이 취소될 수 있습니다.
- 채용 및 업무 수행과 관련하여 요구되는 법령 상 자격이 갖추어지지 않은 경우 채용이 제한될 수 있습니다.
- 보훈 대상자 및 장애인 여부는 채용 과정에서 어떠한 불이익도 미치지 않습니다.
- 담당 업무 범위는 후보자의 전반적인 경력과 경험 등 제반사정을 고려하여 변경될 수 있습니다. 이러한 변경이 필요할 경우, 최종 합격 통지 전 적절한 시기에 후보자와 커뮤니케이션 될 예정입니다.
- 채용 관련 문의사항은 아래 메일 주소로 문의바랍니다.
- [email protected]