Lead the bring-up and debugging of high-speed memory interfaces(e.g., HBM, DDR, LPDDR, GDDR) on advanced SoCs and AI accelerators
Optimize memory interface timings and configurations across multiple DRAM types and vendors to achieve peak performance and reliability
Conduct comprehensive validation, IO tuning, and PVT(Process, Voltage, Temperature) testing of memory subsystems to ensure compliance with design specifications and performance targets
Identify, analyze, and resolve complex issues related to memory subsystems. Collaborate with design and architecture teams to address these issues and enhance system stability
Work closely with pre-silicon design teams to understand new features, develop validation test plans, and ensure seamless integration. Partner with board design, signal integrity, and other engineering teams to deliver robust memory solutions
Develop and validate low-level firmware for memory subsystems using C/C++ and participate in post-silicon testing to ensure functionality
Create detailed technical reports and documentation for validation results, and effectively communicate findings and recommendations to stakeholders
Key Qualifications
In-depth understanding and hands-on experience with memory protocols such as HBM, DDR, LPDDR, and GDDR
Strong programming skills in C/C++ for firmware development and experience with scripting languages like Python or Perl for lab automation
Proven experience in post-silicon bring-up, validation, and debugging of memory subsystems
Familiarity with lab equipment(e.g., oscilloscopes, multimeters, logic analyzers) and a solid understanding of PCB layout, high-speed board design, and signal integrity principles
채용 및 업무 수행과 관련하여 요구되는 법령 상 자격이 갖추어지지 않은 경우 채용이 제한될 수 있습니다.
보훈 대상자 및 장애인 여부는 채용 과정에서 어떠한 불이익도 미치지 않습니다.
담당 업무 범위는 후보자의 전반적인 경력과 경험 등 제반사정을 고려하여 변경될 수 있습니다. 이러한 변경이 필요할 경우, 최종 합격 통지 전 적절한 시기에 후보자와 커뮤니케이션 될 예정입니다.
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DRAM Systems Architect
Responsibilities and Opportunities
Lead the bring-up and debugging of high-speed memory interfaces(e.g., HBM, DDR, LPDDR, GDDR) on advanced SoCs and AI accelerators
Optimize memory interface timings and configurations across multiple DRAM types and vendors to achieve peak performance and reliability
Conduct comprehensive validation, IO tuning, and PVT(Process, Voltage, Temperature) testing of memory subsystems to ensure compliance with design specifications and performance targets
Identify, analyze, and resolve complex issues related to memory subsystems. Collaborate with design and architecture teams to address these issues and enhance system stability
Work closely with pre-silicon design teams to understand new features, develop validation test plans, and ensure seamless integration. Partner with board design, signal integrity, and other engineering teams to deliver robust memory solutions
Develop and validate low-level firmware for memory subsystems using C/C++ and participate in post-silicon testing to ensure functionality
Create detailed technical reports and documentation for validation results, and effectively communicate findings and recommendations to stakeholders
Key Qualifications
In-depth understanding and hands-on experience with memory protocols such as HBM, DDR, LPDDR, and GDDR
Strong programming skills in C/C++ for firmware development and experience with scripting languages like Python or Perl for lab automation
Proven experience in post-silicon bring-up, validation, and debugging of memory subsystems
Familiarity with lab equipment(e.g., oscilloscopes, multimeters, logic analyzers) and a solid understanding of PCB layout, high-speed board design, and signal integrity principles